CWE-1209: Failure to Disable Reserved Bits
Description
The reserved bits in a hardware design are not disabled prior to production. Typically, reserved bits are used for future capabilities and should not support any functional logic in the design. However, designers might covertly use these bits to debug or further develop new capabilities in production hardware. Adversaries with access to these bits will write to them in hopes of compromising hardware state.
Submission Date :
Feb. 6, 2020, midnight
Modification Date :
2023-06-29 00:00:00+00:00
Organization :
Intel Corporation
Extended Description
Reserved bits are labeled as such so they can be allocated for a later purpose. They are not to do anything in the current design. However, designers might want to use these bits to debug or control/configure a future capability to help minimize time to market (TTM). If the logic being controlled by these bits is still enabled in production, an adversary could use the logic to induce unwanted/unsupported behavior in the hardware.
Example - 1
Assume a hardware Intellectual Property (IP) has address space 0x0-0x0F for its configuration registers, with the last one labeled reserved (i.e. 0x0F). Therefore inside the Finite State Machine (FSM), the code is as follows:
gpio_out = 1;
beginend4'b1111 : //0x0Freg gpio_out = 0; //gpio should remain low for normal operationcase (register_address)
//4'b1111 : //0x0Fdefault: gpio_out = gpio_out;reg gpio_out = 0; //gpio should remain low for normal operationcase (register_address)
Related Weaknesses
This table shows the weaknesses and high level categories that are related to this weakness. These relationships are defined to give an overview of the different insight to similar items that may exist at higher and lower levels of abstraction.
Visit http://cwe.mitre.org/ for more details.