Example - 1

For example, consider a design with a 16-bit address that has two software privilege levels: Privileged_SW and Non_privileged_SW. To isolate the system memory regions accessible by these two privilege levels, the design supports three memory regions: Region_0, Region_1, and Region_2.Each region is defined by two 32 bit registers: its range and its access policy.Address_range[15:0]: specifies the Base address of the regionAddress_range[31:16]: specifies the size of the regionAccess_policy[31:0]: specifies what types of software can access a region and which actions are allowedCertain bits of the access policy are defined symbolically as follows:Access_policy.read_np: if set to one, allows reads from Non_privileged_SWAccess_policy.write_np: if set to one, allows writes from Non_privileged_SWAccess_policy.execute_np: if set to one, allows code execution by Non_privileged_SWAccess_policy.read_p: if set to one, allows reads from Privileged_SWAccess_policy.write_p: if set to one, allows writes from Privileged_SWAccess_policy.execute_p: if set to one, allows code execution by Privileged_SWFor any requests from software, an address-protection filter checks the address range and access policies for each of the three regions, and only allows software access if all three filters allow access.Consider the following goals for access control as intended by the designer:Region_0 & Region_1: registers are programmable by Privileged_SWRegion_2: registers are programmable by Non_privileged_SWThe intention is that Non_privileged_SW cannot modify memory region and policies defined by Privileged_SW in Region_0 and Region_1. Thus, it cannot read or write the memory regions that Privileged_SW is using.

<xhtml_p>Non_privileged_SW can program the Address_range register for Region_2 so that its address overlaps with the ranges defined by Region_0 or Region_1. Using this capability, it is possible for Non_privileged_SW to block any memory region from being accessed by Privileged_SW, i.e., Region_0 and Region_1.</xhtml_p>

This design could be improved in several ways.

Ensure that software accesses to memory regions are only permitted if all three filters permit access. Additionally, the scheme could define a memory region priority to ensure that Region_2 (the memory region defined by Non_privileged_SW) cannot overlap Region_0 or Region_1 (which are used by Privileged_SW).

Example - 2

The example code below is taken from the IOMMU controller module of the HACK@DAC'19 buggy CVA6 SoC [REF-1338]. The static memory map is composed of a set of Memory-Mapped Input/Output (MMIO) regions covering different IP agents within the SoC. Each region is defined by two 64-bit variables representing the base address and size of the memory region (XXXBase and XXXLength).

In this example, we have 12 IP agents, and only 4 of them are called out for illustration purposes in the code snippets. Access to the AES IP MMIO region is considered privileged as it provides access to AES secret key, internal states, or decrypted data.

<xhtml_b>localparam logic[63:0] UARTLength = 64'h0011_1000;</xhtml_b>
<xhtml_b>localparam logic[63:0] AESLength = 64'h0000_1000;</xhtml_b>
localparam logic[63:0] PLICLength = 64'h03FF_FFFF;localparam logic[63:0] SPILength = 64'h0080_0000;
...

<xhtml_b>UARTBase = 64'h1000_0000,</xhtml_b>
<xhtml_b>AESBase = 64'h1010_0000,</xhtml_b>
...PLICBase = 64'h0C00_0000,SPIBase = 64'h2000_0000,...typedef enum logic [63:0] {...

The vulnerable code allows the overlap between the protected MMIO region of the AES peripheral and the unprotected UART MMIO region. As a result, unprivileged users can access the protected region of the AES IP. In the given vulnerable example UART MMIO region starts at address 64'h1000_0000 and ends at address 64'h1011_1000 (UARTBase is 64'h1000_0000, and the size of the region is provided by the UARTLength of 64'h0011_1000).

On the other hand, the AES MMIO region starts at address 64'h1010_0000 and ends at address 64'h1010_1000, which implies an overlap between the two peripherals' memory regions. Thus, any user with access to the UART can read or write the AES MMIO region, e.g., the AES secret key.

To mitigate this issue, remove the overlapping address regions by decreasing the size of the UART memory region or adjusting memory bases for all the remaining peripherals. [REF-1339]

<xhtml_b>localparam logic[63:0] UARTLength = 64'h0000_1000;</xhtml_b>
localparam logic[63:0] PLICLength = 64'h03FF_FFFF;localparam logic[63:0] AESLength = 64'h0000_1000;localparam logic[63:0] SPILength = 64'h0080_0000;
...

...PLICBase = 64'h0C00_0000,UARTBase = 64'h1000_0000,AESBase = 64'h1010_0000,SPIBase = 64'h2000_0000,...typedef enum logic [63:0] {...